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| D D D R A FT D D R A FT D R A FT R R A FT A FT LPC2921/2923/2925 Rev. 00.01 -- 24 October 2008 D R A A FT D R A FT D FT D R A D D ARM9 microcontroller with CAN, LIN, and USB device Preliminary data sheet D R A FT FT D R R A FT D R R A FT R A FT R A FT D R FT D R A F R A FT D A 1. General description D The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller, CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, communication, and automotive markets. To optimize system power consumption, the LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. D R A FT D R A 2. Features ARM968E-S processor running at frequencies of up to 125 MHz maximum. Multilayer AHB system bus at 125 MHz with four separate layers. On-chip memory: Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data TCM (DTCM). On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each. On the LPC2923 and LPC2921, one 16 kB SRAM block. 8 kB ETB SRAM, also usable for code execution and data. Up to 512 kB high-speed flash-program memory. 16 kB true EEPROM, byte-erasable/programmable. Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can be used with both I2C interfaces, the SPI interfaces, and the UARTs, as well as for memory-to-memory transfers including the TCM memories. Serial interfaces: USB 2.0 full-speed device controller with dedicated DMA controller and on-chip device PHY. Two-channel CAN controller supporting Full-CAN and extensive message filtering. Two LIN master controllers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces. Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485 (9-bit) support. Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO. Two I2C-bus interfaces. D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Other peripherals: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8 analog inputs each with conversion times as low as 2.44 s per channel. Each channel provides a compare function to minimize interrupts. Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external signal input. Four 32-bit timers each containing four capture-and-compare registers linked to I/Os. Four six-channel PWMs (Pulse-Width Modulators) with capture and trap functionality. Two dedicated 32-bit timers to schedule and synchronize PWM and ADC. Quadrature encoder interface that can monitor one external quadrature encoder. 32-bit watchdog with timer change protection, running on safe clock. Up to 60 general-purpose I/O pins with programmable pull-up, pull-down, or bus keeper. Vectored Interrupt Controller (VIC) with 16 priority levels. Up to 16 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up features. Configurable clock-out pin for driving external system clocks. Processor wake-up from power-down via external interrupt pins; CAN or LIN activity. Flexible Reset Generator Unit (RGU) able to control resets of individual modules. Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules: On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring. On-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz. PLL input range 10 MHz to 25 MHz. On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz. Generation of up to 11 base clocks. Seven fractional dividers. Second, dedicated CGU with its own PLL generates the USB clock and a configurable clock output. Highly configurable system Power Management Unit (PMU): clock control of individual modules. allows minimization of system operating power consumption in any configuration. Standard ARM test and debug interface with real-time in-circuit emulator. Boundary-scan test supported. ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for application code and data storage. Dual power supply: CPU operating voltage: 1.8 V 5 %. I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V. 100-pin LQFP package. -40 C to +85 C ambient operating temperature range. D D R R A A FT D R A FT D D R A FT D D R A D R A D R A D R A R R A D R R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 2 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 3. Ordering information Table 1. Ordering information Package Name LPC2921FBD100 LQFP100 LPC2923FBD100 LQFP100 LPC2925FBD100 LQFP100 Description plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm Type number D D R A FT D D R A FT D R A F R A R Version SOT407-1 SOT407-1 SOT407-1 A FT D R A FT D FT D R A 3.1 Ordering options Table 2. Part options Flash SRAM (incl. USB UART memory ETB SRAM) device RS485 128 kB 256 kB 512 kB 24 kB 24 kB 40 kB yes yes yes 2 2 2 LIN 2.0/ UART 2 2 2 CAN 2 2 2 Package LQFP100 LQFP100 LQFP100 Type number LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 3 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 4. Block diagram JTAG interface D D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A LPC2921/2923/2925 ITCM 16 kB TEST/DEBUG INTERFACE 8 kB SRAM DTCM 16 kB ARM968E-S 1 master 2 slaves master master GPDMA CONTROLLER VECTORED INTERRUPT CONTROLLER AHB TO DTL BRIDGE slave slave GPDMA REGISTERS master CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT AHB TO DTL BRIDGE slave slave USB DEVICE CONTROLLER power. clock, and reset subsystem slave EMBEDDED SRAM 16 kB slave EMBEDDED SRAM 16 kB (LPC2925 only) AHB MULTILAYER MATRIX slave EMBEDDED FLASH 512/256/128 kB slave AHB TO APB BRIDGE general subsystem SYSTEM CONTROL EVENT ROUTER CHIP FEATURE ID AHB TO APB BRIDGE peripheral subsystem 16 kB EEPROM TIMER0/1 MTMR PWM0/1/2/3 3.3 V ADC1/2 QUADRATURE ENCODER AHB TO APB BRIDGE MSC subsystem slave slave GENERAL PURPOSE I/O PORTS 0/1/5 TIMER 0/1/2/3 SPI0/1/2 CAN0/1 GLOBAL ACCEPTANCE FILTER I2C0/1 AHB TO APB BRIDGE slave networking subsystem RS485 UART0/1 WDT 002aae224 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2921/2923/2925 block diagram LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 4 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 5. Pinning information 5.1 Pinning 100 76 D D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A 1 75 LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 25 26 50 51 002aae242 Fig 2. Pin configuration for SOT407-1 (LQFP100) 5.2 Pin description 5.2.1 General description The LPC2921/2923/2925 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and port 5 with 2 pins. Ports 4/3/2 are not used. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section. 5.2.2 LQFP100 pin assignment Table 3. Pin name TDO P0[24]/TXD1/ TXDC1/SCS2[0] P0[25]/RXD1/ RXDC1/SDO2 P0[26]/TXD1/SDI2 P0[27]/RXD1/SCK2 P0[28]/CAP0[0]/ MAT0[0] P0[29]/CAP0[1]/ MAT0[1] VDD(IO) P0[30]/CAP0[2]/ MAT0[2] P0[31]/CAP0[3]/ MAT0[3] VSS(IO) LPC2921_2923_2925_0 LQFP100 pin assignment Pin 1[1] 2[1] 3[1] 4[1] 5[1] 6[1] 7[1] 8 9[1] 10[1] 11 Description Function 0 (default) GPIO 0, pin 24 GPIO 0, pin 25 GPIO 0, pin 26 GPIO 0, pin 27 GPIO 0, pin 28 GPIO 0, pin 29 3.3 V power supply for I/O GPIO 0, pin 30 GPIO 0, pin 31 ground for I/O (c) NXP B.V. 2008. All rights reserved. Function 1 UART1 TXD UART1 RXD - Function 2 CAN1 TXD CAN1 RXD UART1 TXD UART1 RXD TIMER0 CAP0 TIMER0 CAP1 Function 3 SPI2 SCS0 SPI2 SDO SPI2 SDI SPI2 SCK TIMER0 MAT0 TIMER0 MAT1 IEEE 1149.1 test data out - TIMER0 CAP2 TIMER0 CAP3 TIMER0 MAT2 TIMER0 MAT3 Preliminary data sheet Rev. 00.01 -- 24 October 2008 5 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 3. Pin name LQFP100 pin assignment ...continued Pin 12[2] 13[2] 14 15 16 17 18[1] 19[1] 20 21[1] Description Function 0 (default) Function 1 USB_D+ USB_D- Function 2 GPIO 5, pin 19 GPIO 5, pin 18 D Function 3 D R A FT D D R A FT D R A F R A R A FT FT P5[19]/USB_D+ P5[18]/USB_D- VDD(IO) VDD(CORE) VSS(CORE) VSS(IO) P1[27]/CAP1[2]/ TRAP2/PMAT3[3] P1[26]/PMAT2[0]/ TRAP3/PMAT3[2] VDD(IO) P1[25]/PMAT1[0]/ USB_VBUS/ PMAT3[1] P1[24]/PMAT0[0]/ USB_CONNECT/ PMAT3[0] P1[23]/RXD0 P1[22]/TXD0/ USB_UP_LED TMS TCK P1[21]/CAP3[3]/ CAP1[3] P1[20]/CAP3[2]/ SCS0[1] P1[19]/CAP3[1]/ SCS0[2] P1[18]/CAP3[0]/ SDO0 P1[17]/CAP2[3]/ SDI0 VSS(IO) P1[16]/CAP2[2]/ SCK0 P1[15]/CAP2[1]/ SCS0[0] P1[14]/CAP2[0]/ SCS0[3] P1[13]/EI3/SCL1 P1[12]/EI2/SDA1 VDD(IO) P1[11]/SCK1/SCL0 LPC2921_2923_2925_0 - D D R A FT 3.3 V power supply for I/O 1.8 V power supply for digital core ground for core ground for I/O GPIO 1, pin 27 GPIO 1, pin 26 TIMER1 CAP2, ADC2 EXT START PWM2 MAT0 PWM TRAP2 PWM TRAP3 PWM3 MAT3 PWM3 MAT2 D R A 3.3 V power supply for I/O GPIO 1, pin 25 PWM1 MAT0 USB_VBUS PWM3 MAT1 22[1] GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT PWM3 MAT0 23[1] 24[1] 25[1] 26[1] 27[1] 28[1] 29[1] 30[1] 31[1] 32 33[1] 34[1] 35[1] 36[1] 37[1] 38 39[1] GPIO 1, pin 23 GPIO 1, pin 22 UART0 RXD UART0 TXD USB_UP_LED - IEEE 1149.1 test mode select, pulled up internally IEEE 1149.1 test clock GPIO 1, pin 21 GPIO 1, pin 20 GPIO 1, pin 19 GPIO 1, pin 18 GPIO 1, pin 17 ground for I/O GPIO 1, pin 16 GPIO 1, pin 15 GPIO 1, pin 14 GPIO 1, pin 13 GPIO 1, pin 12 TIMER2 CAP2 TIMER2 CAP1 TIMER2 CAP0 EXTINT3 EXTINT2 SPI0 SCK SPI0 SCS0 SPI0 SCS3 I2C1 SCL I2C1 SDA TIMER3 CAP3 TIMER3 CAP2 TIMER3 CAP1 TIMER3 CAP0 TIMER2 CAP3 TIMER1 CAP3, MSCSS PAUSE SPI0 SCS1 SPI0 SCS2 SPI0 SDO SPI0 SDI - 3.3 V power supply for I/O GPIO 1, pin 11 SPI1 SCK I2C0 SCL (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 6 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 3. Pin name LQFP100 pin assignment ...continued Pin 40[1] 41 42 43[1] 44 45[1] 46[1] 47[1] 48[1] 49[1] 50[1] 51[1] 52 53[3] 54[3] 55 56 57 58[1] 59[1] 60[1] 61 62 63[1] 64[1] 65 66[1] 67[1] Description Function 0 (default) Function 1 SPI1 SDI Function 2 I2C0 SDA GPIO 1, pin 10 ground for digital core 1.8 V power supply for digital core GPIO 1, pin 9 ground for I/O GPIO 1, pin 8 GPIO 1, pin 7 GPIO 1, pin 6 GPIO 1, pin 5 GPIO 1, pin 4 SPI1 SCS0 SPI1 SCS3 SPI1 SCS2 SPI1 SCS1 SPI2 SCS2 UART1 RXD UART1 TXD PWM3 MAT5 PWM3 MAT4 SPI1 SDO - D Function 3 D R A FT D D R A FT D R A F R A R A FT FT P1[10]/SDI1/SDA0 VSS(CORE) VDD(CORE) P1[9]/SDO1 VSS(IO) P1[8]/SCS1[0]/ TXDL1/CS0 P1[7]/SCS1[3]/RXD1 P1[6]/SCS1[2]/TXD1 P1[5]/SCS1[1]/ PMAT3[5] P1[4]/SCS2[2]/ PMAT3[4] TRST_N RST_N VSS(OSC_PLL) XOUT_OSC XIN_OSC VDD(OSC_PLL) VSS(OSC_PLL) VDD(IO) P1[3]/SCS2[1]/ PMAT3[3] P1[2]/SCS2[3]/ PMAT3[2] P1[1]/EI1/PMAT3[1] VSS(CORE) VDD(CORE) P1[0]/EI0/PMAT3[0] P0[0]/PHB0/ TXDC0/D24 VSS(IO) P0[1]/PHA0/RXDC0 P0[2]/CLK_OUT/ PMAT0[0] D D R A FT D R A IEEE 1149.1 test reset NOT; active LOW; pulled up internally asynchronous device reset; active LOW; pulled up internally ground for oscillator crystal out for oscillator crystal in for oscillator 1.8 V supply for oscillator and PLL ground for PLL 3.3 V power supply for I/O GPIO 1, pin 3 GPIO 1, pin 2 GPIO 1, pin 1 ground for digital core 1.8 V power supply for digital core GPIO 1, pin 0 GPIO 0, pin 0 ground for I/O GPIO 0, pin 1 GPIO 0, pin 2 GPIO 0, pin 3 GPIO 0, pin 4 GPIO 0, pin 5 GPIO 0, pin 6 GPIO 0, pin 7 QEI0 PHA CLK_OUT USB_UP_LED CAN0 RXD PWM0 MAT0 PWM0 MAT1 PWM0 MAT2 PWM0 MAT3 PWM0 MAT4 PWM0 MAT5 (c) NXP B.V. 2008. All rights reserved. SPI2 SCS1 SPI2 SCS3 EXTINT1 PWM3 MAT3 PWM3 MAT2 PWM3 MAT1 - EXTINT0 QEI0 PHB PWM3 MAT0 CAN0 TXD - P0[3]/USB_UP_LED/ 68[1] PMAT0[1] P0[4]/PMAT0[2] P0[5]/PMAT0[3] VDD(IO) P0[6]/PMAT0[4] P0[7]/PMAT0[5] LPC2921_2923_2925_0 69[1] 70[1] 71 72[1] 73[1] 3.3 V power supply for I/O Preliminary data sheet Rev. 00.01 -- 24 October 2008 7 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 3. Pin name LQFP100 pin assignment ...continued Pin 74 75[1] 76 77[3] 78[3] 79[4] 80[4] 81[4] 82[4] 83 84[4] 85[4] 86[4] 87[4] 88[4] 89[4] 90 91 92 93[4] 94[4] 95[4] 96[4] 97[4] 98 Description Function 0 (default) Function 1 Function 2 3.3 V power supply for ADC D Function 3 D R A FT D D R A FT D R A F R A R A FT FT VDDA(ADC3V3) JTAGSEL N.C. VREFP VREFN P0[8]/IN1[0] P0[9]/IN1[1] P0[10]/IN1[2]/ PMAT1[0] P0[11]/IN1[3]/ PMAT1[1] VSS(IO) P0[12]/IN1[4]/ PMAT1[2] P0[13]/IN1[5]/ PMAT1[3] P0[14]/IN1[6]/ PMAT1[4] P0[15]/IN1[7]/ PMAT1[5] P0[16]IN2[0]/TXD0 P0[17]/IN2[1]/ RXD0/A23 VDD(CORE) VSS(CORE) VDD(IO) P0[18]/IN2[2]/ PMAT2[0] P0[19]/IN2[3]/ PMAT2[1] P0[20]/IN2[4]/ PMAT2[2] P0[21]/IN2[5]/ PMAT2[3] P0[22]/IN2[6]/ PMAT2[4]/A18 VSS(IO) D TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan and flash programming; pulled up internally. not connected HIGH reference for ADC LOW reference for ADC GPIO 0, pin 8 GPIO 0, pin 9 GPIO 0, pin 10 GPIO 0, pin 11 ground for I/O GPIO 0, pin 12 GPIO 0, pin 13 GPIO 0, pin 14 GPIO 0, pin 15 GPIO 0, pin 16 GPIO 0, pin 17 ADC1 IN4 ADC1 IN5 ADC1 IN6 ADC1 IN7 ADC2 IN0 ADC2 IN1 PWM1 MAT2 PWM1 MAT3 PWM1 MAT4 PWM1 MAT5 UART0 TXD UART0 RXD ADC1 IN0 ADC1 IN1 ADC1 IN2 ADC1 IN3 PWM1 MAT0 PWM1 MAT1 - D R A FT D R A 1.8 V power supply for digital core ground for digital core 3.3 V power supply for I/O GPIO 0, pin 18 GPIO 0, pin 19 GPIO 0, pin 20 GPIO 0, pin 21 GPIO 0, pin 22 ground for I/O ADC2 IN2 ADC2 IN3 ADC2 IN4 ADC2 IN5 ADC2 IN6 PWM2 MAT0 PWM2 MAT1 PWM2 MAT2 PWM2 MAT3 PWM2 MAT4 - LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 8 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 3. Pin name LQFP100 pin assignment ...continued Pin 99[4] 100[1] Description Function 0 (default) Function 1 ADC2 IN7 Function 2 PWM2 MAT5 GPIO 0, pin 23 - D Function 3 D R A FT D D R A FT D R A F R A R A FT FT P0[23]/IN2[7]/ PMAT2[5]/A19 TDI [1] [2] [3] [4] D D R A FT IEEE 1149.1 data in, pulled up internally D R A Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up / Pull Down / Repeater. USB pad, 6. Functional description 6.1 Architectural overview The LPC2921/2923/2925 consists of: * An ARM968E-S processor with real-time emulation support * An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers * Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem). * Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems. * One ARM Peripheral Bus for event router and system control. The LPC2921/2923/2925 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place. Completion of a second write to the same subsystem will not be executed until the first write is finished. 6.2 ARM968E-S processor The ARM968E-S is a general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core. Amongst the most compelling features of the ARM968E-S are: * Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 9 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT * Write buffers for the AHB and TCM buses * Enhanced 16 x 32 multiplier capable of single-cycle MAC operations and 16-bit fixedD point DSP instructions to accelerate signal-processing algorithms and applications. R A FT D Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline architecture. Typically, in a three-stage pipeline architecture, while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory. In the five-stage pipeline additional stages are added for memory access and write-back cycles. The ARM968E-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions or to applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM968E-S processor has two instruction sets: D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A R A FT D D R A A FT A FT D R D R A F R A FT D FT D R A FT * Standard 32-bit ARMv5TE set * 16-bit THUMB set The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit controller using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM controller connected to a 16-bit memory system. The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2. 6.3 On-chip flash memory system The LPC2921/2923/2925 includes a 128 kB, 256 kB, or 512 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated on the LPC2921/2923/2925. 6.4 On-chip static RAM In addition to the two 16 kB TCMs, the LPC2921/2923/2925 includes up two static RAM memories of 16 kB each for a total of 32 kB (LPC2925 only) or 1 block of 16 kB (LPC2921/2923). Both may be used for code and/or data storage. The 8 kB SRAM block for the ETB can be used as static memory for code and data storage as well. However, DMA access to this memory region is not supported. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 10 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 6.5 Memory map 4 GB 0xFFFF FFFF 0xFFFF F000 0xFFFF C000 0xFFFF B000 0xFFFF A000 0xFFFF 9000 0xFFFF 8000 0xE00E 0000 0xE00C A000 0xE00C 9000 0xE00C 8000 0xE00C 7000 0xE00C 6000 0xE00C 5000 0xE00C 4000 0xE00C 3000 0xE00C 2000 0xE00C 1000 0xE00C 0000 reserved quadrature encoder PWM3 PWM2 PWM1 PWM0 ADC2 ADC1 reserved MSCSS timer1 MSCSS timer0 remappable to shadow area flash controller reserved 512 kB on-chip flash 256 kB on-chip flash 128 kB on-chip flash reserved flash memory 2 GB peripherals #6 MSCSS subsystem VIC reserved CGU1 PMU RGU CGU0 PCR/VIC subsystem LPC2921/2923/2925 PCR/VIC control reserved DMA interface to TCM reserved ETB control 8 kB ETB SRAM DMA controller USB controller reserved peripheral subsystem #6 0xE00C 0000 reserved 0xE00A 0000 peripheral subsystem #4 reserved peripheral subsystem #2 reserved peripheral subsystem #0 reserved 0x8000 C000 16 kB AHB SRAM (LPC2925 only) reserved 16 kB AHB SRAM 0x2020 4000 0x2020 0000 0x2008 0000 0x2004 0000 0x2002 0000 0x2000 0000 0x2000 0000 no physical memory 0x0080 0000 0x0040 4000 0x0040 0000 0x0000 4000 0x0000 0000 16 kB ITCM 0 GB reserved 16 kB DTCM reserved 512 MB shadow area ITCM/DTCM 0x0000 0000 ITCM/DTCM memory 1 GB reserved on-chip flash 0x2000 0000 0x4000 0000 0x2020 4000 peripherals #0 general subsystem reserved event router SCU CFID 0x8000 8000 0x8000 4000 0x8000 0000 0xE006 0000 0xE008 0000 0xE006 0000 0xE004 0000 0xE002 0000 0xE000 0000 peripherals #2 peripheral subsystem reserved GPIO5 reserved GPIO1 GPIO0 SPI2 SPI1 SPI0 UART1 UART0 TIMER3 TIMER2 TIMER1 TIMER0 WDT 0xE005 0000 0xE004 F000 0xE004 C000 0xE004 B000 0xE004 A000 0xE004 9000 0xE004 8000 0xE004 7000 Preliminary data sheet Rev. 00.01 -- 24 October 2008 11 of 81 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. NXP Semiconductors 0xFFFF FFFF 0xFFFF 8000 0xF080 0000 0xF000 0000 0xE018 3000 0xE018 2000 0xE018 0000 0xE014 0000 0xE010 0000 0xE00E 0000 peripherals #4 networking subsystem 0xE00A 0000 reserved LIN1 LIN0 CAN common regs CAN AF regs CAN ID LUT reserved I2C1 I2C0 CAN1 CAN0 0xE008 B000 0xE008 A000 0xE008 9000 0xE008 8000 0xE008 7000 0xE008 6000 0xE008 4000 0xE008 3000 0xE008 2000 0xE008 1000 0xE008 0000 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F T T ARM9 microcontroller with FT CAN and LIN FT D D D D R R R R A A A 0xE004 6000 0xE004 5000 0xE004 4000 0xE004 3000 0xE004 2000 0xE004 1000 0xE004 0000 0xE002 0000 0xE000 2000 0xE000 2000 0xE000 1000 0xE000 0000 002aae232 LPC2921/2923/2925 FT D R A FT D R A D FT R A FT Fig 3. LPC2921/2923/2925 memory map D R A FT D R A D A FT R FT D R A F D FT D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.6 Reset, debug, test, and power description 6.6.1 Reset and power-up behavior D The LPC2921/2923/2925 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See Section 8 for trip levels of the internal power-up reset circuit1. See Section 9 for characteristics of the several start-up and initialization times. Table 4 shows the reset pin. D Table 4. Symbol RST_N Reset pin Direction IN Description external reset input, active LOW; pulled up internally At activation of the RST_N pin the JTAGSEL pin is sensed as logic LOW. If this is the case the LPC2921/2923/2925 is assumed to be connected to debug hardware, and internal circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment. D R A FT D D R A FT D R A F R A R A FT R A FT D FT D R A 6.6.2 Reset strategy The LPC2921/2923/2925 contains a central module, the Reset Generator Unit (RGU) in the Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards the peripheral modules. The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source. 6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) The LPC2921/2923/2925 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the boundary- scan test pins. Table 5. Symbol JTAGSEL TRST_N TMS TDI TDO TCK IEEE 1149.1 boundary-scan test and debug interface Description TAP controller select input. LOW level selects ARM debug mode and HIGH level selects boundary scan and flash programming; pulled up internally test reset input; pulled up internally (active LOW) test mode select input; pulled up internally test data input, pulled up internally test data output test clock input 1. Only for 1.8 V power sources (c) NXP B.V. 2008. All rights reserved. LPC2921_2923_2925_0 Preliminary data sheet Rev. 00.01 -- 24 October 2008 12 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.6.3.1 ETM/ETB D The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace buffer. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand. The ETB stores trace data produced by the ETM. D R A FT D D R A FT D R A FT D R A FT D FT D R R A F R A The ETM/ETB module has the following features: A * * * * * Closely tracks the instructions that the ARM core is executing. On-chip trace data storage (ETB). All registers are programmed through JTAG interface. Does not consume power when trace is not being used. THUMB/Java instruction set support. 6.6.4 Power supply pins Table 6 shows the power supply pins. Table 6. Symbol VDD(CORE) VSS(CORE) VDD(IO) VSS(IO) VDD(OSC_PLL) VSS(OSC_PLL) VDDA(ADC3V3) Power supply pins Description digital core supply 1.8 V digital core ground (digital core, ADC1/2) I/O pins supply 3.3 V I/O pins ground oscillator and PLL supply oscillator and PLL ground ADC1 and ADC2 3.3 V supply 6.7 Clocking strategy 6.7.1 Clock architecture The LPC2921/2923/2925 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called base clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be unrelated in frequency and phase and can have different clock sources within the CGU. The system clock for the CPU and AHB Bus infrastructure has its own base clock. This means most peripherals are clocked independently from the system clock. See Figure 4 for an overview of the clock areas within the device. Within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. All branch clocks are outputs of the Power Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See Section 6.15 for more details of clock and power control within the device. Two of the base clocks generated by the CGU0 are used as input into a second, dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate the base clock for the USB controller and one base clock for an independent clock output. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 13 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT A FT A FT D R D R A F FT BASE_SYS_CLK BA SE_ICLK0_CLK BASE_USB_CLK D D R A FT R A FT BASE_ICLK1_CLK CPU AHB MULTILAYER MATRIX AHB TO APB BRIDGES D D R A FT D USB R A BASE_OUT_CLK CGU1 CLOCK OUT VIC BASE_IVNSS_CLK networking subsystem GPDMA FLASH/SRAM branch clocks CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0/1 I2C0/1 BASE_PCR_CLK power control subsystem GPIO0/1/5 branch clock RESET/CLOCK GENERATION & POWER MANAGEMENT USB REGISTERS general subsytem SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem branch clocks BASE_TMR_CLK BASE_MSCSS_CLK TIMER 0/1/2/3 BASE_SPI_CLK SPI0/1/2 modulation and sampling control subsystem TIMER0/1 MTMR BASE_UART_CLK UART0/1 BASE_SAFE_CLK WDT branch clocks PWM0/1/2/3 QEI BASE_ADC_CLK branch clocks ADC1/2 CGU0 002aae238 Fig 4. LPC2921/2923/2925 overview of clock areas 6.7.2 Base clock and branch clock relationship Table 7 contains an overview of all the base blocks in the LPC2921/2923/2925 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should not be switched off. See Section 6.15.5 for more details of how to control the individual branch clocks. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 14 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R R A D R R A D A FT A FT D R D FT Table 7. Base clock and branch clock overview Branch clock name CLK_SAFE CLK_SYS_CPU CLK_SYS_SYS CLK_SYS_PCRSS CLK_SYS_FMC CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO5 CLK_SYS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_DMA CLK_SYS_USB R R A FT R A F A FT Base clock BASE_SAFE_CLK BASE_SYS_CLK Parts of the device clocked by this branch clock watchdog timer ARM968E-S and TCMs AHB bus infrastructure Remark [1] D D R A FT D R A FT D A FT D R R AHB side of bridge in PCRSS Flash-Memory Controller Embedded SRAM Controller 0 (16 kB) Embedded SRAM Controller 1 (16 kB) (LPC2925 only) General Subsystem Vectored Interrupt Controller Peripheral Subsystem GPIO bank 0 GPIO bank 1 GPIO bank 5 AHB side of bridge of IVNSS AHB side of bridge of MSCSS GPDMA USB registers PCRSS, CGU, RGU and PMU logic clock APB side of the IVNSS CAN controller Acceptance Filter CAN channel 0 CAN channel 1 I2C0 I2C1 LIN channel 0 LIN channel 1 APB side of the MSCSS Timer 0 in the MSCSS Timer 1 in the MSCSS PWM 0 PWM 1 PWM 2 PWM 3 [1], [3] [2] [4] A BASE_PCR_CLK BASE_IVNSS_CLK CLK_PCR_SLOW CLK_IVNSS_APB CLK_IVNSS_CANCA CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 BASE_MSCSS_CLK CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 CLK_MSCSS_ADC1_APB APB side of ADC 1 CLK_MSCSS_ADC2_APB APB side of ADC 2 CLK_MSCSS_QEI Quadrature encoder LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 15 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 7. Base clock and branch clock overview ...continued Branch clock name CLK_UART0 CLK_UART1 CLK_SPI0 CLK_SPI1 CLK_SPI2 D D R A D R A R A Base clock BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK Parts of the device clocked by this branch clock UART 0 interface clock UART 1 interface clock clock for CGU1 input SPI 0 interface clock SPI 1 interface clock SPI 2 interface clock Remark FT D R A R A FT FT F D R A FT D FT D D R A BASE_TMR_CLK CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 Timer 0 clock for counter part Timer 1 clock for counter part Timer 2 clock for counter part Timer 3 clock for counter part Control of ADC 1, capture sample result Control of ADC 2, capture sample result clock for CGU1 input BASE_ADC_CLK CLK_ADC1 CLK_ADC2 reserved BASE_ICLK1_CLK [1] [2] [3] [4] - This clock is always on (cannot be switched off for system safety reasons) In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock source. See Section 6.12 for details. In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock source. See Section 6.15 for details. The clock should remain activated when system wake-up on timer or UART is required. Table 8. CGU1 base clock and branch clock overview Branch clock name CLK_OUT_CLK CLK_USB_CLK Parts of the device clocked by this branch clock clock out pin USB clock Remark Base clock BASE_OUT_CLK BASE_USB_CLK 6.8 Flash memory controller The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the bootloader. Flash memory contents can be protected by disabling JTAG access. Suspension of burning or erasing is not supported. The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two tasks: * Memory data transfer * Memory configuration via triggering, programming, and erasing The key features are: LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 16 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT * * * * Programming by CPU via AHB Programming by external programmer via JTAG JTAG access protection Burn-finished and erase-finished interrupt D D R A FT D D R A FT D R A F R A R A FT D R A FT D FT 6.8.1 Functional description After reset flash initialization is started. During this initialization, flash access is not possible and AHB transfers to flash are stalled, blocking the AHB bus. During flash initialization, the index sector is read to identify the status of the JTAG access protection and sector security. If JTAG access protection is active, the flash is not accessible via JTAG. In this case, ARM debug facilities are disabled and flash-memory contents cannot be read. If sector security is active, only the unsecured sections can be read. Flash can be read synchronously or asynchronously to the system clock. In synchronous operation, the flash goes into standby after returning the read data. Started reads cannot be stopped, and speculative reading and dual buffering are therefore not supported. With asynchronous reading, transfer of the address to the flash and of read data from the flash is done asynchronously, giving the fastest possible response time. Started reads can be stopped, so speculative reading and dual buffering are supported. Buffering is offered because the flash has a 128-bit wide data interface while the AHB interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash word, from which four words can be read. Without buffering every AHB data port read starts a flash read. A flash read is a slow process compared to the minimum AHB cycle time, so with buffering the average read time is reduced improving system performance. With single buffering, the most recently read flash word remains available until the next flash read. When an AHB data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles. When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer. On a primary buffer, hit data can be copied to the secondary buffer line, which allows the flash to start a speculative read of the next flash word. Both buffer lines are invalidated after: D R A * * * * Initialization Configuration-register access Data-latch reading Index-sector reading The modes of operation are listed in Table 9. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 17 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R R A D R R A D A FT A FT D R D FT Table 9. Flash read modes R R A FT R A F A FT Synchronous timing No buffer line Single buffer line Asynchronous timing No buffer line Single buffer line Dual buffer line, single speculative Dual buffer line, always speculative one flash-word read per word read D for single (non-linear) reads; one flash-word read per word read default mode of operation; most recently read flash word is kept until another flash word is required most recently read flash word is kept until another flash word is required on a buffer miss a flash read is done, followed by at most one speculative read; optimized for execution of code with small loops (less than eight words) from flash most recently used flash word is copied into second buffer line; next flash-word read is started; highest performance for linear reads D R A FT D R A FT D A FT D R A R 6.8.2 Flash layout The ARM processor can program the flash for ISP (In-System Programming) through the flash memory controller. Note that the flash always has to be programmed by `flash words' of 128 bits (four 32-bit AHB bus words, hence 16 bytes). The flash memory is organized into eight `small' sectors of 8 kB each and up to 11 `large' sectors of 64 kB each. The number of large sectors depends on the device type. A sector must be erased before data can be written to it. The flash memory also has sector-wise protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small sector contains 16 pages; a large sector contains 128 pages. Table 10 gives an overview of the flash-sector base addresses. Table 10. Flash sector overview Flash memory address 2000 0000h 2000 2000h 2000 4000h 2000 6000h 2000 8000h 2000 A000h 2000 C000h 2000 E000h 2001 0000h 2002 0000h 2003 0000h 2004 0000h 2005 0000h 2006 0000h 2007 0000h LPC2921 yes yes yes yes yes yes yes yes yes no no no no no no LPC2923 LPC2925 yes yes yes yes yes yes yes yes yes yes yes no no no no yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes Flash memory Sector size (kB) sector number 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 8 8 8 8 8 8 8 8 64 64 64 64 64 64 64 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 18 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector's address space. D D R R A FT D R A Note that the index sector, once programmed, cannot be erased. Any flash operation must be executed out of SRAM (internal or external). D D R A FT D D R A D R A D R A D R A R R A D R R A A FT D FT R A A FT A FT D R D R A F R A FT D FT D FT 6.8.3 Flash bridge wait-states To eliminate the delay associated with synchronizing flash-read data, a predefined number of wait-states must be programmed. These depend on flash-memory response time and system clock period. The minimum wait-states value can be calculated with the following formulas: Synchronous reading: t acc ( clk ) WST > ----------------- - 1 tt tclk ( sys ) R A (1) Asynchronous reading: t acc ( addr ) WST > --------------------- - 1 t tclk ( sys ) (2) Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. 6.8.4 Pin description The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see Section 6.6.3. 6.8.5 Clock description The flash memory controller is clocked by CLK_SYS_FMC, see Section 6.7.2. 6.8.6 EEPROM EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller. 6.9 General Purpose DMA (GPDMA) controller The GPDMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same AHB master or one area by each master. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 19 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT The GPDMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. Incrementing or non-incrementing addressing for source and destination are supported, as well as programmable DMA burst size. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. D D R R A A FT D R A FT D D R A FT D D R A D R A D R A D R A R R A D R R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT 6.9.1 DMA support for peripherals The GPDMA supports the following peripherals: SPI0/1/2, UART0/1, and the I2C0/1-interfaces. The GPDMA can access both embedded SRAM blocks, both TCMs, external static memory, and flash memory. 6.9.2 Clock description The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see Section 6.7.2. 6.10 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host controller. The LPC2921/2923/2925 USB interface includes a device controller with on-chip PHY for device. Details on typical USB interfacing solutions can be found in Section 10.2. 6.10.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. The USB device controller has the following features: * * * * * Fully compliant with USB 2.0 specification (full speed). Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. * Supports SoftConnect and GoodLink features. * While USB is in the Suspend mode, the LPC2921/2923/2925 can enter the reduced power mode and wake up on USB activity. * Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints. * Allows dynamic switching between CPU-controlled slave and DMA modes. * Double buffer implementation for Bulk and Isochronous endpoints. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 20 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.10.2 Pin description Table 11. Pin name USB_VBUS USB device port pins Direction I Description D USB_VBUS status input. When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally. Positive differential data Negative differential data SoftConnect control signal GoodLink LED control signal D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A USB_D+ USB_D- USB_CONNECT USB_UP_LED I/O I/O O O 6.10.3 Clock description Access to the USB registers is clocked by the CLK_SYS_USB, derived from BASE_SYS_CLK, see Section 6.7.2. The CGU1 provides an independent base clock to the USB block, BASE_USB_CLK (see Section 6.15.3). LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 21 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.11 General subsystem 6.11.1 General subsystem clock description D The general subsystem is clocked by CLK_SYS_GESS, see Section 6.7.2. D R A FT D D R A FT D R A F R A R A FT D R A FT D 6.11.2 Chip and feature identification The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains an ID to identify the silicon and also registers containing information about the features enabled or disabled on the chip. The key features are: FT D R A * Identification of product * Identification of features enabled The CFID has no external pins. 6.11.3 System Control Unit (SCU) The system control unit contains system-related functions.The key feature is configuration of the I/O port-pins multiplexer. It defines the function of each I/O pin of the LPC2921/2923/2925. The I/O pin configuration should be consistent with peripheral function usage. The SCU has no external pins. 6.11.4 Event router The event router provides bus-controlled routing of input events to the vectored interrupt controller for use as interrupt or wake-up signals. Key features: * Up to 16 level-sensitive external interrupt pins, including the receive pins of SPI, CAN, LIN, and UART, as well as the I2C-bus SCL pins plus three internal event sources. * Input events can be used as interrupt source either directly or latched (edge-detected). * * * * * Direct events disappear when the event becomes inactive. Latched events remain active until they are explicitly cleared. Programmable input level and edge polarity. Event detection maskable. Event detection is fully asynchronous, so no clock is required. The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. The vectored interrupt-controller inputs are active HIGH. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 22 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.11.4.1 Pin description D The event router module in the LPC2921/2923/2925 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 12 shows the pins connected to the event router. D R A FT D Table 12. Symbol EXTINT 0 - 3 CAN0 RXD CAN1 RXD I2C0_SCL I2C1_SCL USB_D+ LIN0 RXD LIN1 RXD SPI0 SDI SPI1 SDI SPI2 SDI UART0 RXD UART1 RXD Event-router pin connections Direction I I I I I I I I I I I I I na na na Description external interrupt input 0 - 3 CAN0 receive data input wake-up CAN1 receive data input wake-up I2C0 SCL clock input I2C1 SCL clock input USB D+ data input LIN0 receive data input wake-up LIN1 receive data input wake-up SPI0 receive data input SPI1 receive data input SPI2 receive data input UART0 receive data input UART1 receive data input CAN interrupt (internal) VIC FIQ (internal) VIC IRQ (internal) Default polarity 1 0 0 0 0 D R A FT D R A FT D R A FT D FT D R A R A F R A 6.12 Peripheral subsystem 6.12.1 Peripheral subsystem clock description The peripheral subsystem is clocked by a number of different clocks: * * * * * CLK_SYS_PESS CLK_UART0/1 CLK_SPI0/1/2 CLK_TMR0/1/2/3 CLK_SAFE see Section 6.7.2 6.12.2 Watchdog timer The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. Key features: * Internal chip reset if not periodically triggered * Timer counter register runs on always-on safe clock * Optional interrupt generation on watchdog time-out LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 23 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT * Debug mode with disabling of reset * Watchdog control register change-protected with key * Programmable 32-bit watchdog timer period with programmable 32-bit prescaler. D R A FT D R D R A FT D D R A D R A D R A D R A R R A D R R A D R A FT D D FT A A FT A FT D R D R A F R A FT D FT 6.12.2.1 Functional description The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted. When the watchdog times out, it generates a reset through the RGU. To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing to the clear-interrupt register. Another way to prevent resets during debug mode is via the Pause feature of the watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the PAUSE_ENABLE bit in the watchdog timer control register is set. The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains a reset source register to identify the reset source when the device has gone through a reset. See Section 6.15.4. 6.12.2.2 Clock description The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE, see Section 6.7.2. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. R A FT D R A 6.12.3 Timer The LPC2921/2923/2925 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each timer has four capture inputs and/or match outputs. Connection to device pins depends on the configuration programmed into the port function-select registers. The two timers located in the MSCSS have no external capture or match pins, but the memory map is identical, see Section 6.14.6. One of these timers has an external input for a pause function. The key features are: * 32-bit timer/counter with programmable 32-bit prescaler * Up to four 32-bit capture channels per timer. These take a snapshot of the timer value when an external signal connected to the TIMERx CAPn input changes state. A capture event may also optionally generate an interrupt * Four 32-bit match registers per timer that allow: - Continuous operation with optional interrupt generation on match - Stop timer on match with optional interrupt generation - Reset timer on match with optional interrupt generation * Up to four external outputs per timer corresponding to match registers, with the following capabilities: LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 24 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT - Set LOW on match - Set HIGH on match - Toggle on match - Do nothing on match D D R A FT D D R A FT D R A F R A R A FT D R A FT D * Pause input pin (MSCSS timers only) FT D R A The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. They also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt. The core function of the timers consists of a 32 bit prescale counter triggering the 32 bit timer counter. Both counters run on clock CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this clock. Note that each timer has its individual clock source within the Peripheral SubSystem. In the Modulation and Sampling SubSystem each timer also has its own individual clock source. See section Section 6.15.5 for information on generation of these clocks. 6.12.3.1 Pin description The four timers in the peripheral subsystem of the LPC2921/2923/2925 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See Section 6.14.6 for a description of these timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2921/2923/2925, see Section 6.11.3. Table Table 13 shows the timer pins (x runs from 0 to 3). Table 13. Symbol TIMERx CAP[0] TIMERx CAP[1] TIMERx CAP[2] TIMERx CAP[3] TIMERx MAT[0] TIMERx MAT[1] TIMERx MAT[2] TIMERx MAT[3] [1] Timer pins Pin name CAPx[0] CAPx[1] CAPx[2] CAPx[3] MATx[0] MATx[1] MATx[2] MATx[3] Direction IN IN IN IN OUT OUT OUT OUT Description TIMER x capture input 0 TIMER x capture input 1 TIMER x capture input 2 TIMER x capture input 3 TIMER x match output 0 TIMER x match output 1 TIMER x match output 2 TIMER x match output 3 Note that CAP0 and CAP1 are not pinned out on Timer1. 6.12.3.2 Clock description The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx (x = 0-3), see Section 6.7.2. Note that each timer has its own CLK_TMRx branch clock for power management. The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx. 6.12.4 UARTs The LPC2921/2923/2925 contains two identical UARTs located at different peripheral base addresses. The key features are: LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 25 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT * * * * * 16-byte receive and transmit FIFOs. Register locations conform to 550 industry standard. Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes. Built-in baud rate generator. D Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART is commonly used to implement a serial interface such as RS232. The LPC2921/2923/2925 contains two industry-standard 550 UARTs with 16-byte transmit and receive FIFOs, but they can also be put into 450 mode without FIFOs. Remark: The LIN controller can be configured to provide two additional standard UART interfaces (see Section 6.13.2). 6.12.4.1 Pin description The UART pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 14 shows the UART pins (x runs from 0 to 1). Table 14. Symbol UARTx TXD UARTx RXD UART pins Pin name TXDx RXDx Direction OUT IN Description UART channel x transmit data output UART channel x receive data input D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A 6.12.4.2 Clock description The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx (x = 0-1), see Section 6.7.2. Note that each UART has its own CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from the same base clock BASE_CLK_UART. The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. 6.12.5 Serial peripheral interface (SPI) The LPC2921/2923/2925 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: * * * * Master or slave operation Each SPI supports up to four slaves in sequential multi-slave operation Supports timer-triggered operation Programmable clock bit rate and prescale based on SPI source clock (BASE_SPI_CLK), independent of system clock * Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep * Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces * Programmable data-frame size from 4 to 16 bits * Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts * Serial clock-rate master mode: fserial_clk fCLK(SPI)/2 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 26 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT * Serial clock-rate slave mode: fserial_clk = fCLK(SPI)/4 * Internal loopback test mode The SPI module can operate in: D D R A FT D D R A FT D R A F R A R A FT D R FT D * Master mode: - Normal transmission mode - Sequential slave mode A FT D R A * Slave mode 6.12.5.1 Functional description The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces. The SPI module performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with FIFO memories (16 bits wide x 32 words deep). Serial data is transmitted on SPI_TXD and received on SPI_RXD. The SPI module includes a programmable bit-rate clock divider and prescaler to generate the SPI serial clock from the input clock CLK_SPIx. The SPI module's operating mode, frame format, and word size are programmed through the SLVn_SETTINGS registers. A single combined interrupt request SPI_INTREQ output is asserted if any of the interrupts are asserted and unmasked. Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. 6.12.5.2 Pin description The SPI pins are combined with other functions on the port pins of the LPC2921/2923/2925, see Section 6.11.3. Table 15 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3). Table 15. Symbol SPIx SCSy SPIx SCK SPIx SDI SPIx SDO [1] [2] SPI pins Pin name SCSx[y] SCKx SDIx SDOx Direction IN/OUT IN/OUT IN OUT Description SPIx chip select[1][2] SPIx clock[1] SPIx data input SPIx data output Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in slave mode. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 27 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.12.5.3 Clock description D The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx (x = 0, 1, 2), see Section 6.7.2. Note that each SPI has its own CLK_SPIx branch clock for power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx. The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on the interface. D R A FT D D R A FT D R A FT D R A FT D FT D R A R A F R A 6.12.6 General-purpose I/O The LPC2921/2923/2925 contains two general-purpose I/O ports located at different peripheral base addresses. All I/O pins are bidirectional, and the direction can be programmed individually. The I/O pad behavior depends on the configuration programmed in the port function-select registers. The key features are: * * * * 6.12.6.1 General-purpose parallel inputs and outputs Direction control of individual bits Synchronized input sampling for stable input-data values All I/O defaults to input at reset to avoid any possible bus conflicts Functional description The general-purpose I/O provides individual control over each bidirectional port pin. There are two registers to control I/O direction and output level. The inputs are synchronized to achieve stable read-levels. To generate an open-drain output, set the bit in the output register to the desired value. Use the direction register to control the signal. When set to output, the output driver actively drives the value on the output: when set to input the signal floats and can be pulled up internally or externally. 6.12.6.2 Pin description The five GPIO ports in the LPC2921/2923/2925 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 16 shows the GPIO pins. Table 16. Symbol GPIO0 pin[31:0] GPIO1 pin[27:0] GPIO5 pin[19:18] GPIO pins Pin name P0[31:0] P1[27:0] P5[19:18] Direction IN/OUT IN/OUT IN/OUT Description GPIO port x pins 31 to 0 GPIO port x pins 27 to 0 GPIO port x pins 19 and 18 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 28 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.12.6.3 Clock description D The GPIO modules are clocked by several clocks, all of which are derived from BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0, 1, 5), see Section 6.7.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK. D R A D R A FT D R A FT D R A FT D D R A FT D R A F R A FT 6.13 Networking subsystem 6.13.1 CAN gateway Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication. The two CAN controllers in the LPC2921/2923/2925 provide a full implementation of the CAN protocol according to the CAN specification version 2.0B. The gateway concept is fully scalable with the number of CAN controllers, and always operates together with a separate powerful and flexible hardware acceptance filter. The key features are: * * * * * * * * 6.13.1.1 Supports 11-bit as well as 29-bit identifiers Double receive buffer and triple transmit buffer Programmable error-warning limit and error counters with read/write access Arbitration-lost capture and error-code capture with detailed bit position Single-shot transmission (i.e. no re-transmission) Listen-only mode (no acknowledge; no active error flags) Reception of `own' messages (self-reception request) Full CAN mode for message reception Global acceptance filter The global acceptance filter provides look-up of received identifiers - called acceptance filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table memory, in which software maintains one to five sections of identifiers. The CAN ID look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024 standard frame identifiers or 512 extended frame identifiers or a mixture of both types. It is also possible to define identifier groups for standard and extended message formats. 6.13.1.2 Pin description The two CAN controllers in the LPC2921/2923/2925 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 17 shows the CAN pins (x runs from 0 to 1). Table 17. Symbol CANx TXD CANx RXD CAN pins Pin name TXDC0/1 RXDC0/1 Direction OUT IN Description CAN channel x transmit data output CAN channel x receive data input LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 29 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.13.2 LIN D The LPC2921/2923/2925 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2.0 master controllers with additional support for sync break generation and with hardware implementation of the LIN protocol according to spec 2.0. D R A FT D D R A FT D R A FT D R A FT D R A F R A The key features are: FT D R * * * * * * * * * * 6.13.2.1 Complete LIN 2.0 message handling and transfer One interrupt per LIN message Slave response time-out detection Programmable sync-break length Automatic sync-field and sync-break generation Programmable inter-byte space Hardware or software parity generation Automatic checksum generation Fault confinement Fractional baud rate generator A Pin description The two LIN 2.0 master controllers in the LPC2921/2923/2925 have the pins listed below. The LIN pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 18 shows the LIN pins. For more information see Ref. 1 subsection 3.43, LIN master controller. Table 18. Symbol LIN0/1 TXD LIN0/1 RXD LIN controller pins Pin name TXDL0/1 RXDL0/1 Direction OUT IN Description LIN channel 0/1 transmit data output LIN channel 0/1 receive data input Remark: Both LIN channels can be also configured as UART channels. 6.13.3 I2C-bus serial I/O controllers The LPC2921/2923/2925 each contain two I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus, and it can be controlled by more than one bus master connected to it. The main features if the I2C-bus interfaces are: * I2C0 and I2C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus) and do not support powering off of individual devices connected to the same bus lines. * Easy to configure as master, slave, or master/slave. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 30 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT * * * * Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). D Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus. * Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * All I2C-bus controllers support multiple address recognition and a bus monitor mode. 6.13.3.1 Pin description Table 19. Symbol I2C SCL0/1 I2C SDA0/1 [1] D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A I2C-bus pins[1] Pin name SCL0/1 SDA0/1 Direction I/O I/O Description I2C clock input/output I2C data input/output Note that the pins are not I2C-bus compliant open-drain pins. 6.14 Modulation and sampling control subsystem The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2921/2923/2925 includes four Pulse-Width Modulators (PWMs), two 10-bit successive approximation Analog-to-Digital Converters (ADCs) and two timers. The key features of the MSCSS are: * Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various triggerstart options. * Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality. * Two dedicated timers to schedule and synchronize the PWMs and ADCs. * Quadrature encoder interface. 6.14.1 Functional description The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters (ADCs) and timers. Figure 5 provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of communication with the AHB system bus. Two internal timers are dedicated to this subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the first PWM. The second timer (MSCSS timer 1) is used to generate `carrier' signals for the PWMs. These carrier patterns can be used, for example, in applications requiring current control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 31 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. Capture inputs are provided to measure event phases compared to the main counter. Depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. Interrupt signals are generated on several events to closely interact with the CPU. D D R R A A FT D R A FT The ADCs can be used for any application needing accurate digitized data from analog sources. To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section 6.15.2. D R A FT D D R A D R A D R A D R A R R A D R R A FT D D R A A FT A FT D R D R A F R A FT D FT D R A FT LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 32 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D A FT A FT D R D R A F FT AHB-TO-APB BRIDGE D R A FT D R A FT D A FT R MSCSS QEI PHA0 PHB0 D R A capture start MSCSS TIMER0 ADC1 ADC1 IN[7:0] start ADC2 ADC2 EXT START ADC2 IN[7:0] start PWM0 capture carrier synch carrier PAUSE MSCSS TIMER1 carrier PWM1 synch PWM2 carrier synch PWM3 PWM3 MAT[5:0] PWM2 MAT[5:0] PWM1 MAT[5:0] PWM0 MAT[5:0] PWM0 CAP[2:0] PWM1 CAP[2:0] PWM2 TRAP PWM2 CAP[2:0] PWM3 TRAP PWM3 CAP[2:0] 002aae248 Fig 5. Modulation and Sampling Control Sub System (MSCSS) block diagram LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 33 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.14.2 Pin description D The pins of the LPC2921/2923/2925 MSCSS associated with the two ADC modules are described in Section 6.14.4.2. Pins connected to the four PWM modules are described in Section 6.14.5.4, pins directly connected to the MSCSS timer 1 module are described in Section 6.14.6.1, and pins connected to the quadrature encoder interface are described in Section 6.14.7.1. Remark: The IDX0 function for the QEI, the external start function for ADC1, and the TRAP0/1 functions for the PWM0/1 are not pinned out on the LPC2921/2923/2925. D R A FT D D R A FT D R A FT D R A FT D FT D R A R A F R A 6.14.3 Clock description The MSCSS is clocked from a number of different sources: * * * * CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge CLK_MSCSS_APB clocks the subsystem APB bus CLK_MSCSS_MTMR0/1 clocks the timers CLK_MSCSS_PWM0..3 clocks the PWMs. Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 1 or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see Section 6.7.2. All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding clocks can be switched off. 6.14.4 Analog-to-digital converter The MSCSS in the LPC2921/2923/2925 includes two 10-bit successive-approximation analog-to-digital converters. The key features of the ADC interface module are: * ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to 3.3 V. * External reference-level inputs. * 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit resolution. * Programmable resolution from 2-bit to 10-bit. * Single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode. * Optional conversion on transition on external start input, timer capture/match signal, PWM_sync or `previous' ADC. * Converted digital values are stored in a register for each channel. * Optional compare condition to generate a `less than' or an `equal to or greater than' compare-value indication for each channel. * Power-down mode. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 34 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.14.4.1 Functional description D The ADC block diagram, Figure 6, shows the basic architecture of each ADC. The ADC functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain. A mechanism is provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain. The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency. To meet this constraint or to select the desired lower sampling frequency, the clock generation unit provides a programmable fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined by the ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC registers requires an enabled ADC clock, which is controllable via the clock generation unit, see Section 6.15.2. Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs are connected at MSCSS level, see Section 6.14 for details. D R A FT D D R A FT D R A FT D R A FT D FT D R A R A F R A APB clock (BASE_MSCSS_CLK) ADC clock (up to 4.5 MHz) (BASE_ADC_CLK) SYSTEM DOMAIN ADC DOMAIN update APB system bus IRQ scan IRQ compare ADC REGISTERS conversion data configuration data IRQ ADC CONTROL 3.3 V ADC1 ANALOG MUX 3.3 V IN ANALOG MUX 3.3 V IN ADC1 IN[7:0] 3.3 V ADC2 ADC2 IN[7:0] ADC start 0 ADC start 2 ADC start 1 ADC start 3 sync_out 002aae251 Fig 6. ADC block diagram 6.14.4.2 Pin description The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2921/2923/2925. The VREFN and VREFP pins are common for both ADCs. Table 20 shows the ADC pins. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 35 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R R A D R R A D A FT A FT D R D FT Table 20. Symbol Analog to digital converter pins Pin name IN1/2[7:0] Direction IN IN IN IN Description R R A FT D R R A F D R A FT ADC1/2 IN[7:0] analog input for 3.3 V ADC1/2, channel 7 to channel 0 ADC external start-trigger input ADC LOW reference level ADC HIGH reference level A A FT D R FT D ADC2_EXT_START CAP1[2] VREFN VREFP VREFN VREFP A FT D R A Remark: Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see Table 31) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant. 6.14.4.3 Clock description The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and CLK_ADCx (x = 1 or 2), see Section 6.7.2. Note that each ADC has its own CLK_ADCx and CLK_MSCSS_ADCx_APB branch clocks for power management. If an ADC is unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off. The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical since they are derived from the same base clock BASE_ADC_CLK. The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB. Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 6. 6.14.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2921/2923/2925 includes four PWM modules with the following features. * * * * * * Six pulse-width modulated output signals Double edge features (rising and falling edges programmed individually) Optional interrupt generation on match (each edge) Different operation modes: continuous or run-once 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods A protective mode (TRAP) holding the output in a software-controllable state and with optional interrupt generation on a trap event a capture event * Three capture registers and capture trigger pins with optional interrupt generation on * Interrupt generation on match event, capture event, PWM counter overflow or trap event * A burst mode mixing the external carrier signal with internally generated PWM * Programmable sync-delay output to trigger other PWM modules (master/slave behavior) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 36 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.14.5.1 Functional description D The ability to provide flexible waveforms allows PWM blocks to be used in multiple applications; e.g. dimmer/lamp control and fan control. Pulse-width modulation is the preferred method for regulating power since no additional heat is generated, and it is energy-efficient when compared with linear-regulating voltage control networks. D R The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A very basic application of these pulses can be in controlling the amount of power transferred to a load. Since the duty cycle of the pulses can be controlled, the desired amount of power can be transferred for a controlled duration. Two examples of such applications are: * Dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle period allows the PWM to control the amount of power to be transferred to the load. The PWM functions as a dimmer controller in this application * Motor controller: The PWM provides multi-phase outputs, and these outputs can be controlled to have a certain pattern sequence. In this way the force/torque of the motor can be adjusted as desired. This makes the PWM function as a motor drive. D R A FT D R A FT D R A FT D D R A FT D R A F R A A FT sync_in transfer_enable_in APB DOMAIN update APB system bus PWM CONTROL & REGISTERS capture data PWM DOMAIN match outputs PWM, COUNTER, PRESCALE COUNTER & SHADOW REGISTERS capture inputs IRQ pwm PWM counter value IRQ capt_match config data IRQ's trap input carrier inputs transfer_enable_out sync_out 002aad837 Fig 7. PWM block diagram The PWM block diagram in Figure 7 shows the basic architecture of each PWM. PWM functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective. The actual PWM and prescale counters are located in the PWM domain but system control takes place in the APB domain. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 37 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM counter. The position of the rising and falling edges of the PWM outputs can be programmed individually. The prescale counter allows high system bus frequencies to be scaled down to lower PWM periods. Registers are available to capture the PWM counter values on external events. D D R R A A FT D R A FT D Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references are related to the period of this clock. See Section 6.15 for information on generation of these clocks. 6.14.5.2 Synchronizing the PWM counters A mechanism is included to synchronize the PWM period to other PWMs by providing a sync input and a sync output with programmable delay. Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 5 for details of the connections of the PWM modules within the MSCSS in the LPC2921/2923/2925. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. 6.14.5.3 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted. A delay may be inserted between the counter start and generation of trans_enable_out and sync_out. A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 6.14.5.4 Pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2921/2923/2925. Table 21 shows the PWM0 to PWM3 pins (n = 0 to 3). Table 21. Symbol PWMn CAP[0] PWMn CAP[1] PWMn CAP[2] PWMn MAT[0] PWMn MAT[1] PWMn MAT[2] PWMn MAT[3] PWMn MAT[4] PWMn MAT[5] PWMn TRAP PWM pins Pin name PCAPn[0] PCAPn[1] PCAPn[2] PMATn[0] PMATn[1] PMATn[2] PMATn[3] PMATn[4] PMATn[5] TRAPn Direction IN IN IN OUT OUT OUT OUT OUT OUT IN Description PWM n capture input 0 PWM n capture input 1 PWM n capture input 2 PWM n match output 0 PWM n match output 1 PWM n match output 2 PWM n match output 3 PWM n match output 4 PWM n match output 5 PWM n trap input (on the LPC2921/2923/2925 n = 2, 3) (c) NXP B.V. 2008. All rights reserved. D R A FT D D R A D R A D R A D R A R R A D R R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT LPC2921_2923_2925_0 Preliminary data sheet Rev. 00.01 -- 24 October 2008 38 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.14.5.5 Clock description D The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 - 3), see Section 6.7.2. Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power management. The frequency of all these clocks is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK. D R A FT Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer counter registers of the PWM modules run at the same clock as the APB system interface CLK_MSCSS_APB. This clock is independent of the AHB system clock. If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off. D R A FT D R A FT D R A FT D R A FT D R A F D R A 6.14.6 Timers in the MSCSS The two timers in the MSCSS are functionally identical to the timers in the peripheral subsystem, see Section 6.12.3. The features of the timers in the MSCSS are the same as the timers in the peripheral subsystem, but the capture inputs and match outputs are not available on the device pins. These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS, see Section 6.14.1. See section Section 6.12.3 for a functional description of the timers. 6.14.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2921/2923/2925. Table 22 shows the MSCSS timer 1 external pin. Table 22. Symbol MSCSS PAUSE MSCSS timer 1 pin Direction IN Description pause pin for MSCSS timer 1 6.14.6.2 Clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0 to 1), see Section 6.7.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for power management. The frequency of all these clocks is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK. Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter registers run at the same clock as the APB system interface CLK_MSCSS_APB. This clock is independent of the AHB system clock. If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off. 6.14.7 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 39 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT The QEI has the following features: D D R A FT D R A FT F R A * * * * * * * * * * Tracks encoder position. Increments/ decrements depending on direction. Programmable for 2X or 4X position counting. Velocity capture using built-in timer. Velocity compare function with less than interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. D Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. D R A FT D R A FT D A FT D R A R * Digital filter with programmable delays for encoder input signals. * Can accept decoded signal inputs (clk and direction). * Connected to APB. 6.14.7.1 Pin description The QEI module in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2921/2923/2925. Table 23 shows the QEI pins. Table 23. Symbol QEI0 PHA QEI pins Pin name PHA0 Direction IN Description Sensor signal. Corresponds to PHA in quadrature mode and to direction in clock/direction mode. Sensor signal. Corresponds to PHB in quadrature mode and to clock signal in clock/direction mode. QEI0 PHB PHB0 IN Remark: The index function for the QEI is not pinned out on the LPC2921/2923/2925. 6.14.7.2 Clock description The QEI module is clocked by CLK_MSCSS_QEI, see Section 6.7.2. The frequency of this clock is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK. If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off. 6.15 Power, clock, and Reset control Sub System (PCRSS) The Power, Clock, and Reset Control Subsystem (PCRSS) in the LPC2921/2923/2925 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). Figure 8 provides an overview of the PCRSS. An AHB-to-DTL bridge controls the communication with the AHB system bus. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 40 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A CGU0 EXTERNAL OSCILLATOR PLL OUT6 OUT11 PLL LOW POWER RING OSCILLATOR FDIV[6:0] OUT0 OUT1 FDIV CGU1 PMU D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D FT OUT0 OUT2 CLOCK GATES branch clocks R A OUT5 OUT7 AHB master disable: grant request CGU0/1 REGISTERS OUT9 CLOCK ENABLE CONTROL AHB2DTL BRIDGE PMU REGISTERS wakeup_a RGU AHB_RST RGU REGISTERS SCU_RST RESET OUTPUT DELAY LOGIC WARM_RST COLD_RST PCR_RST RGU_RST POR_RST POR INPUT DEGLITCH/ SYNC RST_N (device pin) reset from watchdog counter 002aae249 Fig 8. Power, Clock, and Reset control Sub System (PCRSS) block diagram 6.15.1 Clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see Section 6.7.2. CLK_SYS_PCRSS is derived from BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 41 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.15.2 Clock Generation Unit (CGU0) The key features are: D D R A FT D D R A FT D R A F R A R A * * * * * * * * * * Generation of 11 base clocks selectable from several embedded clock sources. Crystal oscillator with power-down. Control PLL with power-down. Very low-power ring oscillator, always on to provide a safe clock. Seven fractional clock dividers with L/D division. Individual source selector for each base clock, with glitch-free switching. Autonomous clock-activity detection on every clock source. Protection against switching to invalid or inactive clock sources. Embedded frequency counter. FT D R A FT D R A Register write-protection mechanism to prevent unintentional alteration of clocks. Remark: Any clock-frequency adjustment has a direct impact on the timing of all on-board peripherals. 6.15.2.1 Functional description The clock generation unit provides 11 internal clock sources as described in Table 24. Table 24. CGU0 base clocks Frequency (MHz) [1] 0.4 100 0.4 [2] 100 100 160 100 50 100 4.5 160 Description base safe clock (always on) base system clock base PCR subsystem clock base IVNSS subsystem clock base MSCSS subsystem clock base internal clock 0, for CGU1 base UART clock base SPI clock base timers clock base ADCs clock base internal clock 1, for CGU1 FT D Number Name 0 1 2 3 4 5 6 7 8 9 10 11 [1] [2] BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_ICLK0_CLK BASE_UART_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK reserved BASE_ICLK1_CLK Maximum frequency that guarantees stable operation of the LPC2921/2923/2925. Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 42 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D A FT A FT D R D R A F FT CLOCK GENERATION UNIT (CGU0) R R A FT D R A FT D A OUT 0 BASE_SAFE_CLK FT D R A FDIV0 OUT 1 400 kHz LP_OSC clkout clkout120 clkout240 BASE_SYS_CLK EXTERNAL OSCLLLATOR FDIV1 OUT 2 BASE_PCR_CLK PLL OUT 3 BASE_IVNSS_CLK FDIV6 OUT 11 BASE_ICLK1_CLK FREQUENCY MONITOR CLOCK DETECTION AHB TO DTL BRIDGE 002aae147 Fig 9. Block diagram of the CGU0 (see Table 24 for all base clocks) There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 9. LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120 phase-shifted and 240 phase-shifted. Configuration of the CGU0: For every output generator generating the base clocks a choice can be made from the primary and secondary clock generators according to Figure 10. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 43 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D A FT A FT D R D R A F FT LP_OSC FDIV0..6 EXTERNAL OSCILLATOR clkout clkout120 clkout240 D R A FT D R A FT D A FT D R A R PLL OUTPUT CONTROL clock outputs 002aad834 Fig 10. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only LP_OSC as source. The fractional dividers can be connected to one of the outputs of the PLL or directly to LP_OSC/crystal Oscillator. The PLL is connected to the crystal oscillator. In this way every output generating the base clocks can be configured to get the required clock. Multiple output generators can be connected to the same primary or secondary clock source, and multiple secondary clock sources can be connected to the same PLL output or primary clock source. Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL outputs itself for example - will be blocked by hardware. The control register will not be written, the previous value will be kept, although all other fields will be written with new data. This prevents clocks being blocked by incorrect programming. Default Clock Sources: Every secondary clock generator or output generator is connected to LP_OSC at reset. In this way the device runs at a low frequency after reset. It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as (one of) the first step(s) in the boot code after verifying that the high-frequency clock generator is running. Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid, and values of `CLK_SEL' that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock generator. The RDET register keeps track of which clocks are active and inactive, and the LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 44 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT appropriate `CLK_SEL' values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. D R A FT D R Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After reset all clocks are assumed to be `non-present', so the RDET status register will be correct only after 32 BASE_PCR_CLK cycles. Note that this mechanism cannot protect against a currently-selected clock going from active to inactive state. Therefore an inactive clock may still be sent to the system under special circumstances, although an interrupt can still be generated to notify the system. Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators. In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch will occur as quickly as possible, although there will always be a period when the clock is held low due to synchronization requirements. If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the interface. 6.15.2.2 PLL functional description A block diagram of the PLL is shown in Figure 11. The input clock is fed directly to the analog section. This block compares the phase and frequency of the inputs and generates the main clock2. These clocks are either divided by 2 x P by the programmable post divider to create the output clock, or sent directly to the output. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock. D D R A FT D D R A D R A D R A D R A R R A D R R A D R A FT D FT R A A A FT A FT D R D R A F R A FT D FT D R A FT PSEL bits P23EN bit / 2PDIV CCO P23 clkout120 clkout240 clkout input clock bypass direct / MDIV clkout 002aad833 MSEL bits Fig 11. PLL block diagram 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 32, Dynamic characteristics. (c) NXP B.V. 2008. All rights reserved. LPC2921_2923_2925_0 Preliminary data sheet Rev. 00.01 -- 24 October 2008 45 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Triple output phases: For applications that require multiple clock phases two additional clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120 phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown. When the PLL LOCK register is set the second and third phase of the output dividers are synchronized to the main output clock CLKOUT PLL, thus giving three clocks with a 120 phase difference. D Direct output mode: In normal operating mode (with DIRECT set to logic 0) the CCO clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can deviate from 50 %. Power-down control: A Power-down mode has been incorporated to reduce power consumption when the PLL clock is not needed. This is enabled by setting the PD control register bit. In this mode the analog section of the PLL is turned off, the oscillator and the phase-frequency detector are stopped and the dividers enter a reset state. While in Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When Power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal high once it has regained lock on the input clock. 6.15.2.3 Pin description The CGU0 module in the LPC2921/2923/2925 has the pins listed in Table 25 below. Table 25. Symbol XOUT_OSC XIN_OSC CGU0 pins Direction OUT IN Description Oscillator crystal output Oscillator crystal input or external clock input D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT 6.15.3 Clock generation for USB (CGU1) The CGU1 block is functionally identical to the CGU0 block and generates the clock for the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and fractional divider. The PLLs used in CGU0 and CGU1 are identical (see Section 6.15.2.2). The clock input to the CGU1 PLL is provided by one of two base clocks generated in the CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL can be configured to drive the output clock directly. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 46 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D R A FT A FT D R D R A F R FT CLOCK GENERATION UNIT (CGU1) A OUT 0 BASE_USB_CLK A FT D R A FT D FT D R A BASE_ICLK0_CLK BASE_ICLK1_CLK PLL clkout clkout120 clkout240 FDIV0 OUT 2 BASE_OUT_CLK AHB TO DTL BRIDGE 002aae250 Fig 12. Block diagram of the CGU1 6.15.3.1 Pin description The CGU1 module in the LPC2921/2923/2925 has the pins listed in Table 25 below. Table 26. Symbol CLK_OUT CGU1 pins Direction OUT Description clock output 6.15.4 Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: * * * * 6.15.4.1 Reset controlled individually per subsystem Automatic reset stretching and release Monitor function to trace resets back to source Register write-protection mechanism to prevent unintentional resets Functional description Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see Table 27. The first five resets listed in this table form a sort of cascade to provide the multiple levels of impact that a reset may have. The combined input sources are logically OR-ed together so that activating any of the listed reset sources causes the output to go active. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 47 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R R A D R R A D A FT A FT D R D FT Table 27. POR_RST RGU_RST PCR_RST Reset output configuration Reset source power-on reset module POR_RST, RST_N pin PCR_RST COLD_RST COLD_RST COLD_RST COLD_RST COLD_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST R R A FT R A F A FT Reset output Parts of the device reset when activated D D R A FT D LP_OSC; is source for RGU_RST RGU internal; is source for PCR_RST RGU_RST, WATCHDOG PCR internal; is source for COLD_RST parts with COLD_RST as reset source below parts with WARM_RST as reset source below SCU CFID embedded Flash-Memory Controller (FMC) embedded SRAM-Memory Controller GeSS AHB-to-APB bridge PeSS AHB-to-APB bridge all GPIO modules all UART modules all Timer modules in PeSS all SPI modules IVNSS AHB-to-APB bridge all CAN modules including Acceptance filter all LIN modules MSCSS AHB to APB bridge all PWM modules all ADC modules all Timer modules in MSCSS all I2C modules Quadrature encoder DMA controller USB controller Vectored Interrupt Controller (VIC) CPU and AHB Bus infrastructure R A FT D A FT R COLD_RST WARM_RST SCU_RST CFID_RST FMC_RST EMC_RST GESS_A2V_RST PESS_A2V_RST GPIO_RST UART_RST TMR_RST SPI_RST IVNSS_A2V_RST IVNSS_CAN_RST IVNSS_LIN_RST MSCSS_A2V_RST MSCSS_PWM_RST MSCSS_ADC_RST MSCSS_TMR_RST I2C_RST QEI_RST DMA_RST USB_RST VIC_RST AHB_RST D R A 6.15.4.2 Pin description The RGU module in the LPC2921/2923/2925 has the following pins. Table 28 shows the RGU pins. Table 28. Symbol RST_N RGU pins Direction IN Description external reset input, Active LOW; pulled up internally 6.15.5 Power Management Unit (PMU) This module enables software to actively control the system's power consumption by disabling clocks not required in a particular operating mode. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 48 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2921/2923/2925. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming. D D R R A FT D R A D R A FT D D R A D R A D R A D R A R R A D R R A A FT D FT D R A FT A FT D R D R A F R A FT D FT The key features are: A FT D * * * * * * * 6.15.5.1 Individual clock control for all LPC2921/2923/2925 sub-modules Activates sleeping clocks when a wake-up event is detected Clocks can be individually disabled by software Supports AHB master-disable protocol when AUTO mode is set Disables wake-up of enabled clocks when Power-down mode is set Activates wake-up of enabled clocks when a wake-up event is received Status register is available to indicate if an input base clock can be safely switched off (i.e. all branch clocks are disabled) R A Functional description The PMU controls all internal clocks coming out of the CGU0 for power-mode management. With some exceptions, each branch clock can be switched on or off individually under control of software register bits located in its individual configuration register. Some branch clocks controlling vital parts of the device operate in a fixed mode. Table 29 shows which mode- control bits are supported by each branch clock. By programming the configuration register the user can control which clocks are switched on or off, and which clocks are switched off when entering Power-down mode. Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU into power-down should be controlled by disabling the branch clock for the CPU. Remark: For any disabled branch clocks to be re-activated their corresponding base clocks must be running (controlled by the CGU0). Table 29 shows the relation between branch and base clocks, see also Section 6.7.1. Every branch clock is related to one particular base clock: it is not possible to switch the source of a branch clock in the PMU. Table 29. Branch clock overview Legend: `1' Indicates that the related register bit is tied off to logic HIGH, all writes are ignored `0' Indicates that the related register bit is tied off to logic LOW, all writes are ignored `+' Indicates that the related register bit is readable and writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP CLK_SAFE CLK_SYS_CPU CLK_SYS CLK_SYS_PCR CLK_SYS_FMC BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK 0 + + + + AUTO 0 + + + + RUN 1 1 1 1 + (c) NXP B.V. 2008. All rights reserved. LPC2921_2923_2925_0 Preliminary data sheet Rev. 00.01 -- 24 October 2008 49 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Table 29. Branch clock overview ...continued Legend: `1' Indicates that the related register bit is tied off to logic HIGH, all writes are ignored `0' Indicates that the related register bit is tied off to logic LOW, all writes are ignored `+' Indicates that the related register bit is readable and writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP AUTO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RUN + + + + + + + + + + + + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO5 CLK_SYS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_DMA CLK_SYS_USB CLK_PCR_SLOW CLK_IVNSS_APB CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK CLK_MSCSS_ADC2_APB BASE_MSCSS_CLK CLK_MSCSS_QEI CLK_OUT_CLK CLK_UART0 CLK_UART1 CLK_SPI0 CLK_SPI1 CLK_SPI2 LPC2921_2923_2925_0 BASE_MSCSS_CLK BASE_OUT_CLK BASE_UART_CLK BASE_UART_CLK BASE_SPI_CLK BASE_SPI_CLK BASE_SPI_CLK (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 50 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Table 29. Branch clock overview ...continued Legend: `1' Indicates that the related register bit is tied off to logic HIGH, all writes are ignored `0' Indicates that the related register bit is tied off to logic LOW, all writes are ignored `+' Indicates that the related register bit is readable and writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP AUTO + + + + + + 0 + RUN + + + + + + 1 + + + + + + + 0 + D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 CLK_ADC1 CLK_ADC2 CLK_TESTSHELL_IP CLK_USB BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_ADC_CLK BASE_CLK_TESTSHELL BASE_USB_CLK 6.16 Vectored interrupt controller The LPC2921/2923/2925 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request. The key features are: * * * * * * Level-active interrupt request with programmable polarity. 56 interrupt-request inputs. Software-interrupt request capability associated with each request input. Interrupt request state can be observed before masking. Software-programmable priority assignments to interrupt requests up to 15 levels. Software-programmable routing of interrupt requests towards the ARM-processor inputs IRQ and FIQ. * Fast identification of interrupt requests through vector. * Support for nesting of interrupt service routines. 6.16.1 Functional description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: * Target 0 is ARM processor FIQ (fast interrupt service) * Target 1 is ARM processor IRQ (standard interrupt service) Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows: * Priority level 0 corresponds to `masked' (i.e. interrupt requests with priority 0 never lead to an interrupt) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 51 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT * Priority 1 corresponds to the lowest priority * Priority 15 corresponds to the highest priority Software interrupt support is provided and can be supplied for: D * Testing RTOS (Real-Time Operating System) interrupt handling without using device-specific interrupt service routines * Software emulation of an interrupt-requesting device, including interrupts 6.16.2 Clock description The VIC is clocked by CLK_SYS_VIC, see Section 6.7.2. D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 52 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 7. Limiting values Table 30. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Supply pins Ptot VDD(CORE) VDD(OSC_PLL) VDDA(ADC3V3) VDD(IO) IDD ISS total power dissipation core supply voltage oscillator and PLL supply voltage 3.3 V ADC analog supply voltage I/O supply voltage supply current ground current average value per supply pin average value per ground pin [2] [1] D D R A FT D D R A FT D R A F R A R A FT D FT D Parameter Conditions Min -0.5 -0.5 -0.5 -0.5 - Max 1.5 +2.0 +2.0 +4.6 +4.6 98 98 Unit W V V V V mA mA R A FT D R A [2] Input pins and I/O pins VXIN_OSC VI(IO) VI(ADC) VVREFP VVREFN II(ADC) IOHS IOLS General Tstg Tamb storage temperature ambient temperature -65 -40 +150 +85 C C voltage on pin XIN_OSC I/O input voltage ADC input voltage voltage on pin VREFP voltage on pin VREFN ADC input current HIGH-level short-circuit output current LOW-level short-circuit output current average value per input pin drive HIGH, output shorted to VSS(IO) drive LOW, output shorted to VDD(IO) [8] [2] [3][4][6] -0.5 -0.5 -0.5 -0.5 -0.5 for ADC1/2: I/O port 0 pin 8 to pin 23. [4][6] +2.0 VDD(IO) + 3.0 VDDA(ADC3V3) + 0.5 +3.6 +3.6 35 -33 +38 V V V V V mA mA mA Output pins and I/O pins configured as output [8] LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 53 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT Table 30. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol ESD Vesd electrostatic discharge voltage on all pins human body model charged device model on corner pins charged device model [1] [2] [3] [4] [5] [6] [7] [8] Based on package heat transfer, not device power consumption. Peak current must be limited at 25 times average current. For I/O Port 0, the maximum input voltage is defined by VI(ADC). Only when VDD(IO) is present. Not exceeding 6 V. Note that pull-up should be off. With pull-up do not exceed 3.6 V. Human-body model: discharging a 100 pF capacitor via a 10 k series resistor. 112 mA per VDD(IO) or VSS(IO) should not be exceeded. [7] D D R A FT D R A FT F R A Parameter Conditions Min Max Unit D D R R A A FT D R A FT D FT -2000 -500 -750 +2000 +500 +750 V V V D R A LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 54 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 8. Static characteristics D Table 31. Static characteristics VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A FT D D R A FT D R A FT D D R A F R A R A FT Symbol Supplies Core supply VDD(CORE) IDD(CORE) Parameter Conditions Min Typ Max Unit FT D R A core supply voltage core supply current ARM9 and all peripherals active at max clock speeds all clocks off [2] 1.71 - 1.80 1.1 1.89 2.5 V mA/ MHz A V V mA A V mA A V 2.7 1.71 30 1.80 3.3 - 475 3.6 1.89 1 2 3.6 1.9 4 + 5.5 I/O supply VDD(IO) VDD(OSC_PLL) IDD(OSC_PLL) I/O supply voltage oscillator and PLL supply voltage oscillator and PLL supply current normal mode Power-down mode Oscillator/PLL supply 3.0 Analog-to-digital converter supply VDDA(ADC3V3) IDDA(ADC3V3) 3.3 V ADC analog supply voltage 3.3 V ADC analog supply current normal mode Power-down mode all port pins and VDD(IO) applied see Section 7 port 0 pins 8 to 23 when ADC1/2 is used all port pins and VDD(IO) not applied all other I/O pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK VIH HIGH-level input voltage all port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK all port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK [8] [7][8] -0.5 Input pins and I/O pins configured as input VI input voltage VVREFP -0.5 -0.5 +3.6 VDD(IO) V V 2.0 - - V VIL LOW-level input voltage - - 0.8 V Vhys ILIH ILIL LPC2921_2923_2925_0 hysteresis voltage HIGH-level input leakage current LOW-level input leakage current 0.4 - - 1 1 V A A (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 55 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Table 31. Static characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D R A FT A FT D R D R A F R A FT Symbol II(pd) II(pu) Parameter pull-down input current pull-up input current Conditions all port pins, VI = 3.3 V; VI = 5.5 V all port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS: VI = 0 V; VI > 3.6 V is not allowed [3] Min 25 -25 Typ 50 -50 Max 100 -115 Unit A FT A A FT D D R A FT D R A Ci VO VOH VOL CL VVREFN VVREFP VI(ADC) Zi input capacitance output voltage HIGH-level output voltage IOH = -4 mA LOW-level output voltage load capacitance voltage on pin VREFN voltage on pin VREFP ADC input voltage input impedance on port 0 pins between VVREFN and VVREFP between VVREFN and VDD(A5V) IOL = 4 mA 0 VDD(IO) - 0.4 0 VVREFN + 2 VVREFN 4.4 13.7 2 -2 -1 -20 -20 3 - 8 VDD(IO) 0.4 25 VVREFP - 2 VDDA(ADC3V3) VVREFP 23.6 10 +2 +1 +20 +20 pF V V V pF V V V k k bit LSB LSB mV mV Output pins and I/O pins configured as output Analog-to-digital converter supply FSR INL DNL Verr(offset) Verr(FS) full scale range integral non-linearity differential non-linearity offset error voltage full-scale error voltage LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 56 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT Table 31. Static characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT D D R A FT A FT D R D R A F R A FT Symbol Oscillator Rs(xtal) Parameter crystal series resistance Conditions fosc = 10 MHz to 15 MHz Cxtal = 10 pF; Cext = 18 pF Cxtal = 20 pF; Cext = 39 pF fosc = 15 MHz to 20 MHz Cxtal = 10 pF; Cext = 18 pF [5] [5] Min Typ Max Unit A FT D R A FT D FT D - - 160 60 R A [9] - 80 2 pF V V mV Ci Vtrip(high) Vtrip(low) Vtrip(dif) input capacitance high trip level voltage low trip level voltage difference between high and low trip level voltage of XIN_OSC 1.1 1.0 50 1.4 1.3 120 Power-up reset [6] [6] [6] 1.6 1.5 180 [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power-supply voltage range. Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered down. For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input capacitance to ADC. This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or -38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted. Cxtal is crystal load capacitance and Cext are the two external load capacitors. The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 s before reset is de-asserted; VDD(CORE) must be below Vtrip(low) for 11 s before internal reset is asserted. Not 5 V-tolerant when pull-up is on. For I/O Port 0, the maximum input voltage is defined by VI(ADC). This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results. [2] [3] [4] [5] [6] [7] [8] [9] LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 57 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A offset error EO 1023 D R A D R A D R A gain error EG R R A D R R A D R A FT D D R A FT D R A FT A FT A FT D R D R A F R A FT D FT D FT 1022 R A 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDDA - VSSA 1024 002aac046 Fig 13. ADC characteristics LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 58 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 8.1 Power consumption 80 IDD(CORE) (mA) 60 D 002aae241 D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A 40 20 0 10 50 90 core frequency (MHz) 130 Conditions: Tamb = 25 C; active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 14. IDD(CORE) at different core frequencies (active mode) 80 IDD(CORE) (mA) 60 100 MHz 80 MHz 40 125 MHz 002aae240 40 MHz 20 10 MHz 0 1.7 1.8 core voltage (V) 1.9 Conditions: Tamb = 25 C; active mode entered executing code from flash; all peripherals enabled but not configured to run. Fig 15. IDD(CORE) at different core voltages VDD(CORE) (active mode) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 59 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A 80 IDD(CORE) (mA) 60 125 MHz 002aae239 D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT 100 MHz 80 MHz FT D R A 40 40 MHz 20 10 MHz 0 -40 -15 10 35 60 85 temperature (C) Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 16. IDD(CORE) at different temperatures (active mode) 8.2 Electrical pin characteristics X X (X) X 001aac984 X X X X X X X (X) X X X Measured on pins Pn.m; VDDIO = Fig 17. Typical LOW-level output IOLcurrent versus LOW-level output VOL LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 60 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A X X (X) X 001aac984 D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D R FT X X X X X X X (X) X A X X Measured on pins Pn.m; VDDIO = Fig 18. Typical HIGH-level output IOH current versus HIGH-level output voltage VOH X X (X) X 001aac984 X X X X X X X (X) X X X Measured on pins Pn.m; VDDIO = Fig 19. Typical pull-up current Ipu versus input voltage Vi LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 61 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A X X (X) X 001aac984 D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT D R FT X X X X X X X (X) X A X X Measured on pins Pn.m; VDDIO = Fig 20. Typical pull-down current Ipd versus input voltage Vi LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 62 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9. Dynamic characteristics D 9.1 Dynamic characteristics: I/O pins, internal clock, oscillators, PLL, and CAN Table 32. Dynamic characteristics VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] Symbol I/O pins tTHL tTLH Internal clock fclk(sys) Tclk(sys) fref(RO) tstartup Oscillator fi(osc) oscillator input frequency maximum frequency is the clock input of an external clock source applied to the Xin pin at maximum frequency [3] [4] D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A Parameter HIGH-to-LOW transition time LOW-to-HIGH transition time system clock frequency system clock period RO reference frequency start-up time Conditions CL = 30 pF CL = 30 pF Min 4 4 Typ - Max 13.8 13.8 Unit ns ns [2] [2] 10 8 0.36 0.4 6 - 125 100 0.42 100 MHz ns MHz s MHz Low-power ring oscillator at maximum frequency [3] 10 tstartup PLL fi(PLL) fo(PLL) ta(clk) ta(A) tjit(cc)(p-p) start-up time - 500 - s PLL input frequency PLL output frequency CCO; direct mode clock access time address access time cycle to cycle jitter (peak-to-peak value) on CAN TXDC pin [3] 10 10 156 - 0.4 25 160 320 63.4 60.3 1 MHz MHz MHz ns ns ns Jitter specification for CAN [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. See Table 24. This parameter is not part of production testing or final testing, hence only a typical value is stated. Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable. [2] [3] [4] LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 63 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9.2 USB interface Table 33. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3), unless otherwise specified. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 21 must accept as EOP; see Figure 21 [1] D D R A FT D D R A FT D R A F R A R A FT FT Conditions 10 % to 90 % 10 % to 90 % tr / tf Min 8.5 7.7 1.3 Typ - Max 13.8 13.7 109 2.0 175 +5 +18.5 +9 - Unit ns ns % V ns ns ns ns ns D D R A FT D R A see Figure 21 see Figure 21 160 -2 -18.5 -9 40 tEOPR2 EOP width at receiver [1] 82 - - ns [1] Characterized but not implemented as production test. Guaranteed by design. tPERIOD crossover point differential data lines crossover point extended source EOP width: tFEOPT differential data to SE0/EOP skew n x tPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 21. Differential data-to-EOP transition skew and EOP width LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 64 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9.3 Dynamic characteristics: I2C-bus interface D Table 34. Dynamic characteristic: I2C-bus pins VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified[1] D R A FT D D R A FT D R A FT D R F R A R A FT D Symbol tf(o) tr tf tBUF tLOW tHD;STA tHIGH tSU;DAT tSU;STA tSU;STO [1] Parameter output fall time rise time fall time bus free time between a STOP and START condition LOW period of the SCL clock hold time (repeated) START condition HIGH period of the SCL clock data set-up time set-up time for a repeated START condition set-up time for STOP condition Conditions VIH to VIL Min 20 + 0.1 x Typ[2] Max Unit ns A FT D R A - All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Bus capacitance Cb in pF, from 10 pF to 400 pF. [2] [3] SDA t BUF t LOW tr tf t HD;STA SCL P S t HD;STA t HD;STA t HIGH t SU;DAT S t SU;STA P t SU;STO 002aad985 Fig 22. I2C-bus pins clock timing LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 65 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9.4 Dynamic characteristics: SPI D Table 35. Dynamic characteristics of SPI pins VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A FT D D R A FT D R A FT D D R F R A R A FT Symbol fSPI SPI master TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV tSPIOH SPI slave TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV tSPIOH [1] Parameter SPI operating frequency Conditions master operation slave operation Min 1 1 65024fclk(spi) 65024fclk(spi) Typ Max 1 f 2 clk(spi) 1 f 4 clk(spi) Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns A FT D R A SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time - All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. tSPICLK tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIQV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH tSPIOH DATA VALID 002aad986 Fig 23. SPI master timing (CPHA = 1) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 66 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT A FT A FT D R D R A F FT tSPICLK tSPICLKH tSPICLKL D D R A FT R A FT SCK (CPOL = 0) D D R A FT SCK (CPOL = 1) tSPIQV MOSI DATA VALID DATA VALID tSPIDSU DATA VALID tSPIDH tSPIOH D R A MISO DATA VALID 002aad987 Fig 24. SPI master timing (CPHA = 0) tSPICLK tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIQV MISO DATA VALID DATA VALID tSPIDH DATA VALID tSPIOH 002aad988 Fig 25. SPI slave timing (CPHA = 1) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 67 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT A FT A FT D R D R A F FT tSPICLK tSPICLKH tSPICLKL D D R A FT R A FT SCK (CPOL = 0) D D R A FT SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIQV MISO DATA VALID DATA VALID tSPIDH D R A DATA VALID tSPIOH 002aad989 Fig 26. SPI slave timing (CPHA = 0) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 68 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9.5 Dynamic characteristics: flash memory D Table 36. Flash characteristics VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.[1] D R A FT D D R A FT D R A FT D R F R A R A FT D Symbol Nendu tret tprog ter Parameter endurance retention time programming time erase time Conditions number of program/erase cycles average Tamb = 85 C word page global sector Min 10,000 10 95 0.95 - Typ Max Unit A FT D R A cycles years s ms ms ms s ms ns ns ns tinit twr(pg) tfl(BIST) ta(clk) ta(A) [1] initialization time page write time flash word BIST time clock access time address access time All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 69 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 9.6 Dynamic characteristics: ADC1/2 D Table 37. ADC dynamic characteristics VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.[1] D R A FT D D R A FT D R A F R A R A FT D R A FT D FT Symbol fi(ADC) fs(max) Parameter ADC input frequency maximum sampling rate Conditions [2] Min 4 Typ - Max 4.5 Unit MHz D R A fi(ADC) = 4.5 MHz; fs = fi(ADC)/(n + 1) with n = resolution resolution 2 bit resolution 10 bit 3 2 1500 400 11 10 ksampl e/s ksampl e/s cycles bits tconv conversion time In number of ADC clock cycles In number of bits [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Duty cycle clock should be as close as possible to 50 %. [2] 10. Application information 10.1 Operating frequency selection 145 core frequency (MHz) 135 VDD(CORE) = 1.95 V VDD(CORE) = 1.8 V 002aae194 125 VDD(CORE) = 1.65 V 115 105 25 45 65 temperature (C) 85 Fig 27. LPC29xx core operating frequency versus temperature for different core voltages. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 70 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A 145 core frequency (MHz) 135 002aae193 D R A D R A D R A FT R R A D R R A D R A FT D D R A FT D R A A FT A FT D R D R A F R A FT D FT 25 C 45 C 65 C 85 C FT D R A 125 115 105 1.65 1.75 1.85 core voltage (V) 1.95 Fig 28. LPC29xx core operating frequency versus core voltage for different temperatures 10.2 Suggested USB interface solutions VDD(IO) USB_UP_LED USB_CONNECT LPC29xx soft-connect switch R1 1.5 k USB_VBUS USB_D+ RS = 33 USB_D- RS = 33 VSS(IO) 002aae149 USB-B connector Fig 29. LPC2921/2923/2925 USB interface on a self-powered device LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 71 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A R R A D R R A D R A A FT A FT D R D R A FT VDD(IO) FT D R R A FT D R A FT A FT D F FT D R2 D R LPC29xx USB_UP_LED USB_VBUS USB_D+ RS = 33 USB_D- RS = 33 VSS(IO) R1 1.5 k A USB-B connector 002aae150 Fig 30. LPC2921/2923/2925 USB interface on a bus-powered device LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 72 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 11. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm D D R A FT D D R A FT D R A F R A R SOT407-1 A FT D R A FT D FT D R A c y X 75 76 51 50 ZE A e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 31. Package outline (LQFP100) LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 73 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 12. Soldering of SMD packages D This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". R A FT D D R A FT D D R A FT D R A FT D FT D R A F R A 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. R A 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 12.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 74 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 12.4 Reflow soldering Key characteristics in reflow soldering are: D * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to FT D higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window window for a mix of large and small components on one board * Solder paste printing issues including smearing, release, and adjusting the process * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 38 and 39 Table 38. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 39. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 D R A FT D D R A FT D R A F R A R A R A FT D FT D R A Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32. LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 75 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A D R A FT R R A D R R A D R A FT A FT A FT D R D R A F FT temperature maximum peak temperature = MSL limit, damage level D D R A FT D R A FT D A R minimum peak temperature = minimum soldering temperature FT D R A peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 76 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 13. Abbreviations Table 40. AHB BCL BDL CISC DTL SFSP SCL BEL CCO BIST RISC UART APB Abbreviations list Description Advanced High-performance Bus Buffer Control List Buffer Descriptor List Complex Instruction Set Computers Device Transaction Level Abbreviation D SCU Function Select Port x,y (use without the P if there are no x,y) Slot Control List Buffer Entry List Current Controlled Oscillator Built-In Self Test Reduced Instruction Set Computer Universal Asynchronous Receiver Transmitter ARM Peripheral Bus D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A 14. References [1] [2] [3] [4] [5] UM -- LPC2921/2923/2925 user manual ARM -- ARM web site ARM-SSP -- ARM primecell synchronous serial port (PL022) technical reference manual CAN -- ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling LIN -- LIN specification package, revision 2.0 LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 77 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 15. Revision history Table 41. Revision history Release date D Supersedes D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 78 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] D D R A FT D D R A FT D R A F R A R A FT D R FT D Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. A FT D R A Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GoodLink -- is a trademark of NXP B.V. I2C-bus -- logo is a trademark of NXP B.V. SoftConnect -- is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 79 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 18. Contents General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 General description . . . . . . . . . . . . . . . . . . . . . 5 LQFP100 pin assignment . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 9 Architectural overview . . . . . . . . . . . . . . . . . . . 9 ARM968E-S processor . . . . . . . . . . . . . . . . . . . 9 On-chip flash memory system . . . . . . . . . . . . 10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 10 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset, debug, test, and power description . . . 12 Reset and power-up behavior . . . . . . . . . . . . 12 Reset strategy . . . . . . . . . . . . . . . . . . . . . . . . 12 IEEE 1149.1 interface pins (JTAG boundary-scan test). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.6.3.1 ETM/ETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.6.4 Power supply pins . . . . . . . . . . . . . . . . . . . . . 13 6.7 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . 13 6.7.1 Clock architecture . . . . . . . . . . . . . . . . . . . . . . 13 6.7.2 Base clock and branch clock relationship. . . . 14 6.8 Flash memory controller . . . . . . . . . . . . . . . . . 16 6.8.1 Functional description. . . . . . . . . . . . . . . . . . . 17 6.8.2 Flash layout . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8.3 Flash bridge wait-states . . . . . . . . . . . . . . . . . 19 6.8.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 19 6.8.5 Clock description . . . . . . . . . . . . . . . . . . . . . . 19 6.8.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9 General Purpose DMA (GPDMA) controller . . 19 6.9.1 DMA support for peripherals. . . . . . . . . . . . . . 20 6.9.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 20 6.10 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.10.1 USB device controller . . . . . . . . . . . . . . . . . . . 20 6.10.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 21 6.10.3 Clock description . . . . . . . . . . . . . . . . . . . . . . 21 6.11 General subsystem. . . . . . . . . . . . . . . . . . . . . 22 6.11.1 General subsystem clock description . . . . . . . 22 6.11.2 Chip and feature identification . . . . . . . . . . . . 22 6.11.3 System Control Unit (SCU). . . . . . . . . . . . . . . 22 6.11.4 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.11.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 23 6.12 Peripheral subsystem . . . . . . . . . . . . . . . . . . . 23 1 2 3 3.1 4 5 5.1 5.2 5.2.1 5.2.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.12.1 6.12.2 6.12.2.1 6.12.2.2 6.12.3 6.12.3.1 6.12.3.2 6.12.4 6.12.4.1 6.12.4.2 6.12.5 6.12.5.1 6.12.5.2 6.12.5.3 6.12.6 6.12.6.1 6.12.6.2 6.12.6.3 6.13 6.13.1 6.13.1.1 6.13.1.2 6.13.2 6.13.2.1 6.13.3 6.13.3.1 6.14 6.14.1 6.14.2 6.14.3 6.14.4 6.14.4.1 6.14.4.2 6.14.4.3 6.14.5 6.14.5.1 6.14.5.2 6.14.5.3 6.14.5.4 6.14.5.5 6.14.6 6.14.6.1 6.14.6.2 6.14.7 6.14.7.1 6.14.7.2 6.15 D Peripheral subsystem clock description. . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Serial peripheral interface (SPI). . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . General-purpose I/O . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Networking subsystem. . . . . . . . . . . . . . . . . . CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . Global acceptance filter . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus serial I/O controllers . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Modulation and sampling control subsystem . Functional description . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Analog-to-digital converter . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulator (PWM). . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Synchronizing the PWM counters . . . . . . . . . Master and slave mode . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Timers in the MSCSS. . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Quadrature Encoder Interface (QEI) . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Clock description . . . . . . . . . . . . . . . . . . . . . . Power, clock, and Reset control Sub System (PCRSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . D R A FT D D R A FT 23 23 24 24 24 25 25 25 26 26 26 27 27 28 28 28 28 29 29 29 29 29 30 30 30 31 31 31 34 34 34 35 35 36 36 37 38 38 38 39 39 39 39 39 40 40 40 R A D R A FT D R A F R A FT D FT D R A continued >> LPC2921_2923_2925_0 (c) NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 -- 24 October 2008 80 of 81 D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT D R A FT D D R A D R A D R A D R A R R A D R R A A FT A FT D R FT 6.15.1 Clock description . . . . . . . . . . . . . . . . . . . . . . 41 6.15.2 Clock Generation Unit (CGU0) . . . . . . . . . . . . 42 6.15.2.1 Functional description. . . . . . . . . . . . . . . . . . . 42 6.15.2.2 PLL functional description . . . . . . . . . . . . . . . 45 6.15.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 46 6.15.3 Clock generation for USB (CGU1) . . . . . . . . . 46 6.15.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 47 6.15.4 Reset Generation Unit (RGU). . . . . . . . . . . . . 47 6.15.4.1 Functional description. . . . . . . . . . . . . . . . . . . 47 6.15.4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 48 6.15.5 Power Management Unit (PMU). . . . . . . . . . . 48 6.15.5.1 Functional description. . . . . . . . . . . . . . . . . . . 49 6.16 Vectored interrupt controller . . . . . . . . . . . . . . 51 6.16.1 Functional description. . . . . . . . . . . . . . . . . . . 51 6.16.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 52 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 53 8 Static characteristics. . . . . . . . . . . . . . . . . . . . 55 8.1 Power consumption . . . . . . . . . . . . . . . . . . . . 59 8.2 Electrical pin characteristics . . . . . . . . . . . . . . 60 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 63 9.1 Dynamic characteristics: I/O pins, internal clock, oscillators, PLL, and CAN. . . . . . . . . . . . . . . . 63 9.2 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.3 Dynamic characteristics: I2C-bus interface. . . 65 9.4 Dynamic characteristics: SPI . . . . . . . . . . . . . 66 9.5 Dynamic characteristics: flash memory . . . . . 69 9.6 Dynamic characteristics: ADC1/2 . . . . . . . . . 70 10 Application information. . . . . . . . . . . . . . . . . . 70 10.1 Operating frequency selection . . . . . . . . . . . . 70 10.2 Suggested USB interface solutions . . . . . . . . 71 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 73 12 Soldering of SMD packages . . . . . . . . . . . . . . 74 12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 74 12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 74 12.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 74 12.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 75 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 78 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 79 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 79 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17 Contact information. . . . . . . . . . . . . . . . . . . . . 79 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 D Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. D R A FT D D R A FT D R A F R A R A FT D R A FT D FT D R A (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 October 2008 Document identifier: LPC2921_2923_2925_0 |
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